//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

MEMC_BASE		EQU		0x48000000
SDRAM0_BASE		EQU		0xA0000000
SDRAM1_BASE		EQU		0xA8000000
OSCR_BASE		EQU		0x40A00010
FPGA_REGS_BASE	EQU		0x08000000

; RELEVANT REGISTER-SPECIFIC OFFSETS

;
; MEMC
;
MDCNFG_OFFSET       EQU		0x0
MDREFR_OFFSET       EQU		0x4
MSC0_OFFSET         EQU		0x8
MSC1_OFFSET         EQU		0xC
MSC2_OFFSET         EQU		0x10
MECR_OFFSET         EQU		0x14
SXCNFG_OFFSET       EQU		0x1C
FLYCNFG_OFFSET      EQU		0x20
MCMEM0_OFFSET       EQU		0x28
MCMEM1_OFFSET       EQU		0x2C
MCATT0_OFFSET       EQU		0x30
MCATT1_OFFSET       EQU		0x34
MCIO0_OFFSET        EQU		0x38
MCIO1_OFFSET        EQU		0x3C
MDMRS_OFFSET        EQU		0x40
BOOT_DEF_OFFSET     EQU		0x44
ARB_CNTL_OFFSET     EQU		0x48
BSCNTR0_OFFSET      EQU		0x4C
BSCNTR1_OFFSET      EQU		0x50
LCDBSCNTR_OFFSET    EQU		0x54
MDMRSLP_OFFSET      EQU		0x58
BSCNTR2_OFFSET      EQU		0x5C
BSCNTR3_OFFSET      EQU		0x60

;
; FULL-FEATURE UART
;
FFTHR_OFFSET        EQU     0x0       ; DLAB = 0  WO  8bit - Transmit Holding Register
FFRBR_OFFSET        EQU     0x0       ; DLAB = 0  RO  8bit - Recieve Buffer Register
FFDLL_OFFSET        EQU     0x0       ; DLAB = 1  RW  8bit - Divisor Latch Low Register
FFIER_OFFSET        EQU     0x4       ; DLAB = 0  RW  8bit - Interrupt Enable Register
FFDLH_OFFSET        EQU     0x4       ; DLAB = 1  RW  8bit - Divisor Latch High Register
FFIIR_OFFSET        EQU     0x8       ; DLAB = X  RO  8bit - Interrupt Identification Register
FFFCR_OFFSET        EQU     0x8       ; DLAB = X  WO  8bit - FIFO Control Register
FFLCR_OFFSET        EQU     0xC       ; DLAB = X  RW  8bit - Line Control Register
FFMCR_OFFSET        EQU     0x10      ; DLAB = X  RW  8bit - Modem Control Regiser
FFLSR_OFFSET        EQU     0x14      ; DLAB = X  RO  8bit - Line Status Register
FFMSR_OFFSET        EQU     0x18      ; DLAB = X  RO  8bit - Modem Status Register
FFSPR_OFFSET        EQU     0x1C      ; DLAB = X  RW  8bit - Scratchpad Register
FFISR_OFFSET        EQU     0x20      ; DLAB = X  RW  8bit - Slow Infrared Select Register
FFFOR_OFFSET        EQU     0x24      ; DLAB = X  RO  FIFO Occupancy Register
FFABR_OFFSET        EQU     0x28      ; DLAB = X  RW  Autobaud Control Register
FFACR_OFFSET        EQU     0x2C      ; DLAB = X  Autobaud Count Register

;
; BLUETOOTH UART
;
BTTHR_OFFSET        EQU     0x0       ; DLAB = 0  WO  8bit - Transmit Holding Register
BTRBR_OFFSET        EQU     0x0       ; DLAB = 0  RO  8bit - Recieve Buffer Register
BTDLL_OFFSET        EQU     0x0       ; DLAB = 1  RW  8bit - Divisor Latch Low Register
BTDLH_OFFSET        EQU     0x4       ; DLAB = 1  RW  8bit - Divisor Latch High Register
BTIIR_OFFSET        EQU     0x8       ; DLAB = X  RO  8bit - Interrupt Identification Register
BTIER_OFFSET        EQU     0x4       ; DLAB = 0  RW  8bit - Interrupt Enable Register
BTFCR_OFFSET        EQU     0x8       ; DLAB = X  WO  8bit - FIFO Control Register
BTLCR_OFFSET        EQU     0xC       ; DLAB = X  RW  8bit - Line Control Register
BTMCR_OFFSET        EQU     0x10      ; DLAB = X  RW  8bit - Modem Control Regiser
BTLSR_OFFSET        EQU     0x14      ; DLAB = X  RO  8bit - Line Status Register
BTMSR_OFFSET        EQU     0x18      ; DLAB = X  RO  8bit - Modem Status Register
BTSPR_OFFSET        EQU     0x1C      ; DLAB = X  RW  8bit - Scratchpad Register
BTISR_OFFSET        EQU     0x20      ; DLAB = X  RW  8bit - Slow Infrared Select Register
BTFOR_OFFSET        EQU     0x24      ; DLAB = X  RO  FIFO Occupancy Register
BTABR_OFFSET        EQU     0x28      ; DLAB = X  RW  Autobaud Control Register
BTACR_OFFSET        EQU     0x2C      ; DLAB = X  Autobaud Count Register

;
; STANDARD UART
;
STTHR_OFFSET        EQU     0x0       ; DLAB = 0  WO  8bit - Transmit Holding Register
STRBR_OFFSET        EQU     0x0       ; DLAB = 0  RO  8bit - Recieve Buffer Register
STDLL_OFFSET        EQU     0x0       ; DLAB = 1  RW  8bit - Divisor Latch Low Register
STIER_OFFSET        EQU     0x4       ; DLAB = 0  RW  8bit - Interrupt Enable Register
STDLH_OFFSET        EQU     0x4       ; DLAB = 1  RW  8bit - Divisor Latch High Register
STIIR_OFFSET        EQU     0x8       ; DLAB = X  RO  8bit - Interrupt Identification Register
STFCR_OFFSET        EQU     0x8       ; DLAB = X  WO  8bit - FIFO Control Register
STLCR_OFFSET        EQU     0xC       ; DLAB = X  RW  8bit - Line Control Register
STMCR_OFFSET        EQU     0x10      ; DLAB = X  RW  8bit - Modem Control Regiser
STLSR_OFFSET        EQU     0x14      ; DLAB = X  RO  8bit - Line Status Register
STMSR_OFFSET        EQU     0x18      ; DLAB = X  RO  8bit - Modem Status Register
STSPR_OFFSET        EQU     0x1C      ; DLAB = X  RW  8bit - Scratchpad Register
STISR_OFFSET        EQU     0x20      ; DLAB = X  RW  8bit - Slow Infrared Select Register
STFOR_OFFSET        EQU     0x24      ; DLAB = X  RO  FIFO Occupancy Register
STABR_OFFSET        EQU     0x28      ; DLAB = X  RW  Autobaud Control Register
STACR_OFFSET        EQU     0x2C      ; DLAB = X  Autobaud Count Register

;
; RTC
;
RCNR_OFFSET         EQU     0x0       ; RTC count register
RTAR_OFFSET         EQU     0x4       ; RTC alarm register
RTSR_OFFSET         EQU     0x8       ; RTC status register
RTTR_OFFSET         EQU     0xC       ; RTC timer trim register
RDCR_OFFSET         EQU     0x10      ; RTC Day Counter
RYCR_OFFSET         EQU     0x14      ; RTC Year Counter
RDAR1_OFFSET        EQU     0x18      ; RTC Day Alarm 1
RYAR1_OFFSET        EQU     0x1C      ; RTC Year Alarm 1
RDAR2_OFFSET        EQU     0x20      ; RTC Day Alarm 2
RYAR2_OFFSET        EQU     0x24      ; RTC Year Alarm 2
SWCR_OFFSET         EQU     0x28      ; RTC Stopwatch Counter
SWAR1_OFFSET        EQU     0x2C      ; RTC Stopwatch Alarm 1
SWAR2_OFFSET        EQU     0x30      ; RTC Stopwatch Alarm 2
PICR_OFFSET         EQU     0x34      ; RTC Periodic Interrupt Counter
PIAR_OFFSET         EQU     0x38      ; RTC Periodic Interrupt Alarm

;
; OST (OS TIMER)
;
OSMR0_OFFSET        EQU     0x0       ; OS timer match register 0
OSMR1_OFFSET        EQU     0x4       ; OS timer match register 1
OSMR2_OFFSET        EQU     0x8       ; OS timer match register 2
OSMR3_OFFSET        EQU     0xC       ; OS timer match register 3
OSCR0_OFFSET        EQU     0x10      ; OS timer counter register 0
OSSR_OFFSET         EQU     0x14      ; OS timer status register
OWER_OFFSET         EQU     0x18      ; OS timer watchdog enable register
OIER_OFFSET         EQU     0x1C      ; OS timer interrupt enable register
OSCR4_OFFSET        EQU     0x40
OSCR5_OFFSET        EQU     0x44
OSCR6_OFFSET        EQU     0x48
OSCR7_OFFSET        EQU     0x4C
OSCR8_OFFSET        EQU     0x50
OSCR9_OFFSET        EQU     0x54
OSCR10_OFFSET       EQU     0x58
OSCR11_OFFSET       EQU     0x5C
OSMR4_OFFSET        EQU     0x80
OSMR5_OFFSET        EQU     0x84
OSMR6_OFFSET        EQU     0x88
OSMR7_OFFSET        EQU     0x8C
OSMR8_OFFSET        EQU     0x90
OSMR9_OFFSET        EQU     0x94
OSMR10_OFFSET       EQU     0x98
OSMR11_OFFSET       EQU     0x9C
OMCR4_OFFSET        EQU     0xC0
OMCR5_OFFSET        EQU     0xC4
OMCR6_OFFSET        EQU     0xC8
OMCR7_OFFSET        EQU     0xCC
OMCR8_OFFSET        EQU     0xD0
OMCR9_OFFSET        EQU     0xD4
OMCR10_OFFSET       EQU     0xD8
OMCR11_OFFSET       EQU     0xDC

;
; INTC (INTERRUPT CONTROLLER) - Memory-mapped addresses (can also use c-proc for most of these)
;
ICIP_OFFSET         EQU     0x0       ; Interrupt controller IRQ pending register
ICMR_OFFSET         EQU     0x4       ; Interrupt controller mask register
ICLR_OFFSET         EQU     0x8       ; Interrupt controller level register
ICFP_OFFSET         EQU     0xC       ; Interrupt controller FIQ pending register
ICPR_OFFSET         EQU     0x10      ; Interrupt controller pending register
ICCR_OFFSET         EQU     0x14      ; Interrupt controller control register
ICHP_OFFSET         EQU     0x18      ; Interrupt controller Highest Priority register
IPR0_OFFSET         EQU     0x1C      ; Interrupt controller Priority registerS [31:0]
IPR1_OFFSET         EQU     0x20
IPR2_OFFSET         EQU     0x24
IPR3_OFFSET         EQU     0x28
IPR4_OFFSET         EQU     0x2C
IPR5_OFFSET         EQU     0x30
IPR6_OFFSET         EQU     0x34
IPR7_OFFSET         EQU     0x38
IPR8_OFFSET         EQU     0x3C
IPR9_OFFSET         EQU     0x40
IPR10_OFFSET        EQU     0x44
IPR11_OFFSET        EQU     0x48
IPR12_OFFSET        EQU     0x4C
IPR13_OFFSET        EQU     0x50
IPR14_OFFSET        EQU     0x54
IPR15_OFFSET        EQU     0x58
IPR16_OFFSET        EQU     0x5C
IPR17_OFFSET        EQU     0x60
IPR18_OFFSET        EQU     0x64
IPR19_OFFSET        EQU     0x68
IPR20_OFFSET        EQU     0x6C
IPR21_OFFSET        EQU     0x70
IPR22_OFFSET        EQU     0x74
IPR23_OFFSET        EQU     0x78
IPR24_OFFSET        EQU     0x7C
IPR25_OFFSET        EQU     0x80
IPR26_OFFSET        EQU     0x84
IPR27_OFFSET        EQU     0x88
IPR28_OFFSET        EQU     0x8C
IPR29_OFFSET        EQU     0x90
IPR30_OFFSET        EQU     0x94
IPR31_OFFSET        EQU     0x98

;
; GPIO
;
GPLR0_OFFSET        EQU     0x0        ; GPIO pin-level register 31:0
GPLR1_OFFSET        EQU     0x4        ; GPIO pin-level register 63:32
GPLR2_OFFSET        EQU     0x8        ; GPIO pin-level register 95:64
GPDR0_OFFSET        EQU     0xC        ; GPIO pin-direction register 31:0
GPDR1_OFFSET        EQU     0x10       ; GPIO pin-direction register 63:32
GPDR2_OFFSET        EQU     0x14       ; GPIO pin-direction register 95:64
GPSR0_OFFSET        EQU     0x18       ; GPIO pin output set register 31:0
GPSR1_OFFSET        EQU     0x1C       ; GPIO pin output set register 63:32
GPSR2_OFFSET        EQU     0x20       ; GPIO pin output set register 95:64
GPCR0_OFFSET        EQU     0x24       ; GPIO pin output clear register 31:0
GPCR1_OFFSET        EQU     0x28       ; GPIO pin output clear register 63:32
GPCR2_OFFSET        EQU     0x2C       ; GPIO pin output clear register 95:64
GRER0_OFFSET        EQU     0x30       ; GPIO rising edge detect register 31:0
GRER1_OFFSET        EQU     0x34       ; GPIO rising edge detect register 63:32
GRER2_OFFSET        EQU     0x38       ; GPIO rising edge detect register 95:64
GFER0_OFFSET        EQU     0x3C       ; GPIO falling edge detect register 31:0
GFER1_OFFSET        EQU     0x40       ; GPIO falling edge detect register 63:32
GFER2_OFFSET        EQU     0x44       ; GPIO falling edge detect register 95:64
GEDR0_OFFSET        EQU     0x48       ; GPIO edge detect status register 31:0
GEDR1_OFFSET        EQU     0x4C       ; GPIO edge detect status register 63:32
GEDR2_OFFSET        EQU     0x50       ; GPIO edge detect status register 95:64
GAFR0_L_OFFSET      EQU     0x54       ; GPIO alternate funciton select register 15:0
GAFR0_U_OFFSET      EQU     0x58       ; GPIO alternate function select register 31:16
GAFR1_L_OFFSET      EQU     0x5C       ; GPIO alternate function select register 47:32
GAFR1_U_OFFSET      EQU     0x60       ; GPIO alternate function select register 63:48
GAFR2_L_OFFSET      EQU     0x64       ; GPIO alternate function select register 79:64
GAFR2_U_OFFSET      EQU     0x68       ; GPIO alternate function select register 95:80
GAFR3_L_OFFSET      EQU     0x6C       ; GPIO alternate function select register 111:96
GAFR3_U_OFFSET      EQU     0x70       ; GPIO alternate function select register 120:112
GPLR3_OFFSET        EQU     0x100      ; GPIO pin-level register 120:96
GPDR3_OFFSET        EQU     0x10C      ; GPIO pin-direction register 120:96
GPSR3_OFFSET        EQU     0x118      ; GPIO pin output set register 120:96
GPCR3_OFFSET        EQU     0x124      ; GPIO pin output clear register 120:96
GRER3_OFFSET        EQU     0x130      ; GPIO rising edge detect register 120:96
GFER3_OFFSET        EQU     0x13C      ; GPIO falling edge detect register 120:96
GEDR3_OFFSET        EQU     0x148      ; GPIO edge detect status register 120:96

;
; POWER MANAGER & RESET CONTROLLER
;
PMCR_OFFSET         EQU     0x0        ; Power manager control register
PSSR_OFFSET         EQU     0x4        ; Power manager sleep status register
PSPR_OFFSET         EQU     0x8        ; Power manager scratch pad register
PWER_OFFSET         EQU     0xC        ; Power manager wake-up enable register
PRER_OFFSET         EQU     0x10       ; Power manager GPIO rising edge detect enable register
PFER_OFFSET         EQU     0x14       ; Power manager GPIO falling edge detect enable register
PEDR_OFFSET         EQU     0x18       ; Power manager GPIO edge detect status register
PCFR_OFFSET         EQU     0x1C       ; Power manager general configuration register
PGSR0_OFFSET        EQU     0x20       ; Power manager GPIO sleep state register for GPIO 31:0
PGSR1_OFFSET        EQU     0x24       ; Power manager GPIO sleep state register for GPIO 63:32
PGSR2_OFFSET        EQU     0x28       ; Power manager GPIO sleep state register for GPIO 95:64
PGSR3_OFFSET        EQU     0x2C       ; Power manager GPIO sleep state register for GPIO 120:96
RCSR_OFFSET         EQU     0x30       ;  **Reset controller status register**
PSLR_OFFSET         EQU     0x34       ; Power manager Sleep Mode Config
PSTR_OFFSET         EQU     0x38       ; Power manager Standby Mode Config
PSNR_OFFSET         EQU     0x3C       ; Power manager Sense Mode Config
PVCR_OFFSET         EQU     0x40       ; Power manager Voltage Change Control
PCMD0_OFFSET        EQU     0x80       ; Power manager I2C Command[31:0]
PCMD1_OFFSET        EQU     0x84
PCMD2_OFFSET        EQU     0x88
PCMD3_OFFSET        EQU     0x8C
PCMD4_OFFSET        EQU     0x90
PCMD5_OFFSET        EQU     0x94
PCMD6_OFFSET        EQU     0x98
PCMD7_OFFSET        EQU     0x9C
PCMD8_OFFSET        EQU     0xA0
PCMD9_OFFSET        EQU     0xA4
PCMD10_OFFSET       EQU     0xA8
PCMD11_OFFSET       EQU     0xAC
PCMD12_OFFSET       EQU     0xB0
PCMD13_OFFSET       EQU     0xB4
PCMD14_OFFSET       EQU     0xB8
PCMD15_OFFSET       EQU     0xBC
PCMD16_OFFSET       EQU     0xC0
PCMD17_OFFSET       EQU     0xC4
PCMD18_OFFSET       EQU     0xC8
PCMD19_OFFSET       EQU     0xCC
PCMD20_OFFSET       EQU     0xD0
PCMD21_OFFSET       EQU     0xD4
PCMD22_OFFSET       EQU     0xD8
PCMD23_OFFSET       EQU     0xDC
PCMD24_OFFSET       EQU     0xE0
PCMD25_OFFSET       EQU     0xE4
PCMD26_OFFSET       EQU     0xE8
PCMD27_OFFSET       EQU     0xEC
PCMD28_OFFSET       EQU     0xF0
PCMD29_OFFSET       EQU     0xF4
PCMD30_OFFSET       EQU     0xF8
PCMD31_OFFSET       EQU     0xFC
PIBMR_OFFSET        EQU     0x180      ; Power manager I2C Bus Monitor
PIDBR_OFFSET        EQU     0x188      ; Power manager I2C Data Buffer
PI2CR_OFFSET        EQU     0x190      ; Power manager I2C Control
PISR_OFFSET         EQU     0x198      ; Power manager I2C Status
PISAR_OFFSET        EQU     0x1A0      ; Power manager I2C Slave Address

;
; CLK MAN
;
CCCR_OFFSET         EQU     0x0        ; Core Clock Configuration Register
CKEN_OFFSET         EQU     0x4        ; Clock Enable Register
OSCC_OFFSET         EQU     0x8        ; Oscillator Configuration Register
CCSR_OFFSET         EQU     0xC        ; Core Clock Status

CLKCFG_T			EQU     0x1        ; Turbo mode
CLKCFG_F			EQU     0x2        ; Frequnce change
CLKCFG_B			EQU     0x8        ; Fast-bus mode

;
; BMAN:  inserted fwXsc1.inc here.  Not going to have this for bvd, since is really unnecessary
;
RCSR_ALL            EQU	    0x1F       ; bman: EAS 1.5 is a bit unclear   is bit 4 reserved or not? If so, then this value should be 0xF
Mode_SVC	        EQU	    0x13
Mode_USR		    EQU	    0x10
NoIntsMask          EQU	    0x000000C0
IRQIntsMask	        EQU	    0x7F       ; 0=enabled, 1=disabled
IrqFiqEnable        EQU	    0xFFFFFF3F

;
; FLASH constants
;
K3_128Mb_DEVCODE    EQU     0x8806
J3_128Mb_DEVCODE    EQU     0x18

;
; Reset Controller Status Register bit defines
;
RCSR_HARD_RESET     EQU    (0x1)
RCSR_WDOG_RESET     EQU    (0x1 << 1)
RCSR_SLEEP_RESET    EQU    (0x1 << 2)
RCSR_GPIO_RESET     EQU    (0x1 << 3)
PSSR_VALID_MASK     EQU    0x3F
PSSR_RDH            EQU    (0x1 << 5)
PSSR_PH             EQU    (0x1 << 4)

;
; Clock Manager Defs
;
OSCC_OOK            EQU    (0x1)
OSCC_OON            EQU    (0x1 << 1)
OSCC_TOUT_EN        EQU    (0x1 << 2)
OSCC_PIO_EN         EQU    (0x1 << 3)
OSCC_CRI            EQU    (0x1 << 4)
CKEN_DEFAULT        EQU    0x00400240        ; MEMC, OST, FFUART clocked.  Rest OFF

;
;  Power Manager Defs
;
PCFR_OPDE           EQU    (0x1)
PCFR_FP             EQU    (0x1 << 1)
PCFR_FS             EQU    (0x1 << 2)
PCFR_GPR_EN         EQU    (0x1 << 4)
PCFR_SYSEN_EN       EQU    (0x1 << 5)
PCFR_PI2C_EN        EQU    (0x1 << 6)
PCFR_DC_EN          EQU    (0x1 << 7)
PCFR_FVC            EQU    (0x1 << 10)
PCFR_L1_EN          EQU    (0x1 << 11)
PCFR_GP_ROD         EQU    (0x1 << 12)
PWER_WE0            EQU    (0x1)
PWER_WE1            EQU    (0x1 << 1)
PWER_WBB            EQU    (0x1 << 25)
PWER_WEUSBC         EQU    (0x1 << 26)
PWER_WEUSBH0        EQU    (0x1 << 27)
PWER_WEUSBH1        EQU    (0x1 << 28)
PWER_WEP1           EQU    (0x1 << 30)
PWER_WERTC          EQU    (0x1 << 31)
PMCR_BIDAE          EQU    (0x1)
PMCR_BIDAS          EQU    (0x1 << 1)
PMCR_VIDAE          EQU    (0x1 << 2)
PMCR_VIDAS          EQU    (0x1 << 3)
PMCR_IAS            EQU    (0x1 << 4)
PMCR_INTRS          EQU    (0x1 << 5)

;
; Bits used for Memory Controller Init
;
; register bit masks - mdcnfg
BIT0				EQU    (1 << 0)
BIT1				EQU    (1 << 1)
BIT2				EQU    (1 << 2)
BIT3				EQU    (1 << 3)
BIT4				EQU    (1 << 4)
BIT5				EQU    (1 << 5)
BIT6				EQU    (1 << 6)
BIT7				EQU    (1 << 7)
BIT8				EQU    (1 << 8)
BIT9				EQU    (1 << 9)
BIT10				EQU    (1 << 10)
BIT11				EQU    (1 << 11)
BIT12				EQU    (1 << 12)
BIT13				EQU    (1 << 13)
BIT14				EQU    (1 << 14)
BIT15				EQU    (1 << 15)
BIT16				EQU    (1 << 16)
BIT17				EQU    (1 << 17)
BIT18				EQU    (1 << 18)
BIT19				EQU    (1 << 19)
BIT20				EQU    (1 << 20)
BIT21				EQU    (1 << 21)
BIT22				EQU    (1 << 22)
BIT23				EQU    (1 << 23)
BIT24				EQU    (1 << 24)
BIT25				EQU    (1 << 25)
BIT26				EQU    (1 << 26)
BIT27				EQU    (1 << 27)
BIT28				EQU    (1 << 28)
BIT29				EQU    (1 << 29)
BIT30				EQU    (1 << 30)
BIT31				EQU    (1 << 31)

MDCNFG_DE0          EQU    (BIT0)
MDCNFG_DE1          EQU    (BIT1)
MDCNFG_DWID0        EQU    (BIT2)
MDCNFG_DCAC0        EQU    (BIT3 + BIT4)
MDCNFG_DRAC0        EQU    (BIT5 + BIT6)
MDCNFG_DNB0         EQU    (BIT7)
MDCNFG_DTC0         EQU    (BIT8 + BIT9)
MDCNFG_DADDR0       EQU    (BIT10)
MDCNFG_DLATCH0      EQU    (BIT11)
MDCNFG_RESERVED0    EQU    (BIT12 + BIT13 + BIT14 + BIT15)
MDCNFG_DE2          EQU    (BIT16)
MDCNFG_DE3          EQU    (BIT17)
MDCNFG_DWID2        EQU    (BIT18)
MDCNFG_DCAC2        EQU    (BIT19 + BIT20)
MDCNFG_DRAC2        EQU    (BIT21 + BIT22)
MDCNFG_DNB2         EQU    (BIT23)
MDCNFG_DTC2         EQU    (BIT24 + BIT25)
MDCNFG_DADDR2       EQU    (BIT26)
MDCNFG_DLATCH2      EQU    (BIT27)
MDCNFG_RESERVED2    EQU    (BIT28 + BIT29 + BIT30 + BIT31)

MDREFR_E0PIN        EQU    0x00001000
MDREFR_K0RUN        EQU    0x00002000
MDREFR_K1RUN        EQU    0x00010000
MDREFR_K2RUN        EQU    0x00040000
MDREFR_SLFRSH       EQU    0x00400000
MDREFR_E1PIN        EQU    0x00008000
MDREFR_K1DB2        EQU    0x00020000		; run SDCLK[1] @ .5(MClk)
MDREFR_K0DB2        EQU    0x00004000
MDREFR_K0DB4        EQU    0x20000000       ; run SDCLK[0] @ .25(MemClk)
MDREFR_K0FREE       EQU    0x00800000
MDREFR_K1FREE       EQU    0x01000000
MDREFR_K2FREE       EQU    0x02000000
MDREFR_APD          EQU    0x00100000
BANK_SHIFT          EQU    20

;
; Core Clock
;
CCCR       			EQU    (0x41300000)  	; Core Clock Configuration Register
CKEN       			EQU    (0x41300004)  	; Clock Enable Register
OSCC       			EQU    (0x41300008)  	; Oscillator Configuration Register
CCSR				EQU	   (0x4130000C)  	; Core Clock Status Register

;
; CCCR 'L' vals
;
CCCR_L02            EQU    0x2
CCCR_L03            EQU    0x3
CCCR_L04            EQU    0x4
CCCR_L05            EQU    0x5
CCCR_L06            EQU    0x6
CCCR_L07            EQU    0x7
CCCR_L08            EQU    0x8
CCCR_L09            EQU    0x9
CCCR_L10            EQU    0xA
CCCR_L11            EQU    0xB
CCCR_L12            EQU    0xC
CCCR_L13            EQU    0xD
CCCR_L14            EQU    0xE
CCCR_L15            EQU    0xF
CCCR_L16            EQU    0x10
CCCR_L17            EQU    0x11
CCCR_L18            EQU    0x12
CCCR_L19            EQU    0x13
CCCR_L20            EQU    0x14
CCCR_L21            EQU    0x15
CCCR_L22            EQU    0x16
CCCR_L23            EQU    0x17
CCCR_L24            EQU    0x18
CCCR_L25            EQU    0x19
CCCR_L26            EQU    0x1A
CCCR_L27            EQU    0x1B
CCCR_L28            EQU    0x1C
CCCR_L29            EQU    0x1D
CCCR_L30            EQU    0x1E
CCCR_L31            EQU    0x1F

;
; CCCR 'N' vals
;
CCCR_N1p0          EQU    (0x2 << 7)
CCCR_N1p5          EQU    (0x3 << 7)
CCCR_N2p0          EQU    (0x4 << 7)
CCCR_N2p5          EQU    (0x5 << 7)
CCCR_N3p0          EQU    (0x6 << 7)
CCCR_A			   EQU    (0x1 << 25)

;
;  OSC/Clock Defs
;
PLATFORM_MEMORY    EQU    CCCR_L27
CCCR_M1			   EQU	 (0x020)
CCCR_M2			   EQU	 (0x040)
CCCR_N20		   EQU   (0x200)
CORE_CLK_100MHZ    EQU   (PLATFORM_MEMORY + CCCR_M1 + CCCR_N20)
CORE_CLK_200MHZ    EQU   (PLATFORM_MEMORY + CCCR_M2 + CCCR_N20)

OSSR_M3			   EQU   (1 << 3)			; Match status channel 3
OSSR_M2			   EQU   (1 << 2)			; Match status channel 2
OSSR_M1			   EQU   (1 << 1)			; Match status channel 1
OSSR_M0			   EQU   (1 << 0)			; Match status channel 0

OWER_WME		   EQU   (1 << 0)			; Watchdog Match Enable

OIER_E3			   EQU   (1 << 3)			; Interrupt enable channel 3
OIER_E2			   EQU   (1 << 2)			; Interrupt enable channel 2
OIER_E1			   EQU   (1 << 1)			; Interrupt enable channel 1
OIER_E0			   EQU   (1 << 0)			; Interrupt enable channel 0

;
; Bits used for CP 15
;
CONTROL_MMU        EQU    0x00000001

;
; Bits for CKEN
;
CKEN22_MEMC	       EQU    (1 << 22) 	; Memory controler
CKEN16_LCD	       EQU    (1 << 16)	    ; LCD Unit Clock Enable
CKEN14_I2C	       EQU    (1 << 14)	    ; I2C Unit Clock Enable
CKEN13_FICP	       EQU    (1 << 13)	    ; FICP Unit Clock Enable
CKEN12_MMC	       EQU    (1 << 12)	    ; MMC Unit Clock Enable
CKEN11_USB	       EQU    (1 << 11)	    ; USB Unit Clock Enable
CKEN9_OSTIMER	   EQU    (1 << 9)	    ; OS Timer Unit Clock Enable
CKEN8_I2S	       EQU    (1 << 8)	    ; I2S Unit Clock Enable
CKEN7_BTUART	   EQU    (1 << 7)	    ; BTUART Unit Clock Enable
CKEN6_FFUART	   EQU    (1 << 6)	    ; FFUART Unit Clock Enable
CKEN5_STUART	   EQU    (1 << 5)	    ; STUART Unit Clock Enable
CKEN4_HWUART	   EQU    (1 << 4)	    ; HWUART Unit Clock Enable
CKEN3_SSP	       EQU    (1 << 3)	    ; SSP Unit Clock Enable
CKEN2_AC97	       EQU    (1 << 2)	    ; AC97 Unit Clock Enable
CKEN1_PWM1	       EQU    (1 << 1)	    ; PWM1 Clock Enable
CKEN0_PWM0	       EQU    (1 << 0)	    ; PWM0 Clock Enable

;
; Shifts for MSC0/1/2
;
MSC_RBUFFx		   EQU 	  15		; 15,    Return data BUFFer vs. streaming behavior
MSC_RRRx		   EQU 	  14		; 14:12, ROM/SRAM Recovery time
MSC_RDNx		   EQU 	  11		; 11:8,  ROM Delay Next access
MSC_RDFx		   EQU 	  7	    	; 7:4,   The ROM Delay First access field is encoded
MSC_RBWx		   EQU 	  3	    	; 3,     RBWx ROM bus width
MSC_RTx			   EQU 	  2	    	; 2:0,   Rom Type

MSC_RBW_16		   EQU 	  0
MSC_RBW_32		   EQU 	  1

MSC_RT_ROM		   EQU 	  0
MSC_RT_SRAM		   EQU 	  1
MSC_RT_BURST4	   EQU    2
MSC_RT_BURST8	   EQU    3
MSC_RT_VLIO		   EQU    4

FCR_ITL2	       EQU   (1 << 7)	; Interrupt Trigger Level
FCR_ITL1	       EQU   (1 << 6)	; Interrupt Trigger Level
FCR_RESETTF	       EQU   (1 << 2)	; Reset Transmitter FIFO
FCR_RESETRF	       EQU   (1 << 1)	; Reset Receiver FIFO
FCR_TRFIFOE	       EQU   (1 << 0)	; Transmit and Receive FIFO Enable
FCR_ITL_1	       EQU   (0)
FCR_ITL_8	       EQU   (FCR_ITL1)
FCR_ITL_16	       EQU   (FCR_ITL2)
FCR_ITL_32	       EQU   (FCR_ITL2|FCR_ITL1)

LCR_DLAB	       EQU   (1 << 7)	; Divisor Latch Access Bit
LCR_SB		       EQU   (1 << 6)	; Set Break
LCR_STKYP	       EQU   (1 << 5)	; Sticky Parity
LCR_EPS		       EQU   (1 << 4)	; Even Parity Select
LCR_PEN		       EQU   (1 << 3)	; Parity Enable
LCR_STB		       EQU   (1 << 2)	; Stop Bit
LCR_WLS1	       EQU   (1 << 1)	; Word Length Select
LCR_WLS0	       EQU   (1 << 0)	; Word Length Select

LSR_FIFOE	       EQU   (1 << 7)	; FIFO Error Status
LSR_TEMT	       EQU   (1 << 6)	; Transmitter Empty
LSR_TDRQ	       EQU   (1 << 5)	; Transmit Data Request
LSR_BI		       EQU   (1 << 4)	; Break Interrupt
LSR_FE		       EQU   (1 << 3)	; Framing Error
LSR_PE		       EQU   (1 << 2)	; Parity Error
LSR_OE		       EQU   (1 << 1)	; Overrun Error
LSR_DR		       EQU   (1 << 0)	; Data Ready

MCR_AFE		       EQU   (1 << 5)	; Autoflow Control Enable
MCR_LOOP	       EQU   (1 << 4)	; Loopback mode
MCR_OUT2	       EQU   (1 << 3)	; force MSR_DCD in loopback mode
MCR_OUT1	       EQU   (1 << 2)	; force MSR_RI in loopback mode
MCR_RTS		       EQU   (1 << 1)	; Request to Send
MCR_DTR		       EQU   (1 << 0)	; Data Terminal Ready

MSR_DCD		       EQU   (1 << 7)	; Data Carrier Detect
MSR_RI		       EQU   (1 << 6)	; Ring Indicator
MSR_DSR		       EQU   (1 << 5)	; Data Set Ready
MSR_CTS		       EQU   (1 << 4)	; Clear To Send
MSR_DDCD	       EQU   (1 << 3)	; Delta Data Carrier Detect
MSR_TERI	       EQU   (1 << 2)	; Trailing Edge Ring Indicator
MSR_DDSR	       EQU   (1 << 1)	; Delta Data Set Ready
MSR_DCTS	       EQU   (1 << 0)	; Delta Clear To Send

;
; Interrupt Controller
;
ICIP			   EQU   (0x40D00000)  ; Interrupt Controller IRQ Pending Register
ICMR			   EQU   (0x40D00004)  ; Interrupt Controller Mask Register
ICLR			   EQU   (0x40D00008)  ; Interrupt Controller Level Register
ICFP			   EQU   (0x40D0000C)  ; Interrupt Controller FIQ Pending Register
ICPR			   EQU   (0x40D00010)  ; Interrupt Controller Pending Register
ICCR			   EQU   (0x40D00014)  ; Interrupt Controller Control Register

;
; GPIO registers
;
GPLR0			   EQU   (0x40E00000)  ; GPIO Pin-Level Register GPIO<31:0>
GPLR1			   EQU   (0x40E00004)  ; GPIO Pin-Level Register GPIO<63:32>
GPLR2			   EQU   (0x40E00008)  ; GPIO Pin-Level Register GPIO<95:64>

GPDR0			   EQU   (0x40E0000C)  ; GPIO Pin Direction Register GPIO<31:0>
GPDR1			   EQU   (0x40E00010)  ; GPIO Pin Direction Register GPIO<63:32>
GPDR2			   EQU   (0x40E00014)  ; GPIO Pin Direction Register GPIO<95:64>

GPSR0			   EQU   (0x40E00018)  ; GPIO Pin Output Set Register GPIO<31:0>
GPSR1			   EQU   (0x40E0001C)  ; GPIO Pin Output Set Register GPIO<63:32>
GPSR2			   EQU   (0x40E00020)  ; GPIO Pin Output Set Register GPIO<95:64>

GPCR0			   EQU   (0x40E00024)  ; GPIO Pin Output Clear Register GPIO<31:0>
GPCR1			   EQU   (0x40E00028)  ; GPIO Pin Output Clear Register GPIO <63:32>
GPCR2			   EQU   (0x40E0002C)  ; GPIO Pin Output Clear Register GPIO <95:64>

GRER0			   EQU   (0x40E00030)  ; GPIO Rising-Edge Detect Register GPIO<31:0>
GRER1			   EQU   (0x40E00034)  ; GPIO Rising-Edge Detect Register GPIO<63:32>
GRER2			   EQU   (0x40E00038)  ; GPIO Rising-Edge Detect Register GPIO<95:64>

GFER0			   EQU   (0x40E0003C)  ; GPIO Falling-Edge Detect Register GPIO<31:0>
GFER1			   EQU   (0x40E00040)  ; GPIO Falling-Edge Detect Register GPIO<63:32>
GFER2			   EQU   (0x40E00044)  ; GPIO Falling-Edge Detect Register GPIO<95:64>

GEDR0			   EQU   (0x40E00048)  ; GPIO Edge Detect Status Register GPIO<31:0>
GEDR1			   EQU   (0x40E0004C)  ; GPIO Edge Detect Status Register GPIO<63:32>
GEDR2			   EQU   (0x40E00050)  ; GPIO Edge Detect Status Register GPIO<95:64>

GAFR0_L			   EQU   (0x40E00054)  ; GPIO Alternate Function Select Register GPIO<15:0>
GAFR0_U			   EQU   (0x40E00058)  ; GPIO Alternate Function Select Register GPIO<31:16>
GAFR1_L			   EQU   (0x40E0005C)  ; GPIO Alternate Function Select Register GPIO<47:32>
GAFR1_U			   EQU   (0x40E00060)  ; GPIO Alternate Function Select Register GPIO<63:48>
GAFR2_L			   EQU   (0x40E00064)  ; GPIO Alternate Function Select Register GPIO<79:64>
GAFR2_U			   EQU   (0x40E00068)  ; GPIO Alternate Function Select Register GPIO <95:80>
GAFR3_L			   EQU   (0x40E0006C)  ; GPIO Alternate Function Select Register GPIO<111:96>
GAFR3_U			   EQU   (0x40E00070)  ; GPIO Alternate Function Select Register GPIO <120:112>

GPLR3			   EQU   (0x40E00100)  ; GPIO Pin-Level Register GPIO<120:96>
GPDR3			   EQU   (0x40E0010C)  ; GPIO Pin Direction Register GPIO<120:96>
GPSR3			   EQU   (0x40E00118)  ; GPIO Pin Output Set Register GPIO<120:96>
GPCR3			   EQU   (0x40E00124)  ; GPIO Pin Output Clear Register GPIO <120:96>
GRER3			   EQU   (0x40E00130)  ; GPIO Rising-Edge Detect Register GPIO<120:96>
GFER3			   EQU   (0x40E0013C)  ; GPIO Falling-Edge Detect Register GPIO<120:96>
GEDR3			   EQU   (0x40E00148)  ; GPIO Edge Detect Status Register GPIO<120:96>

;
; OS Timer Registers
;
OSMR0			   EQU   (0x40A00000)
OSMR1			   EQU   (0x40A00004)
OSMR2			   EQU   (0x40A00008)
OSMR3			   EQU   (0x40A0000C)
OSCR			   EQU   (0x40A00010)  ; OS Timer Counter Register
OSSR			   EQU   (0x40A00014)  ; OS Timer Status Register
OWER			   EQU   (0x40A00018)  ; OS Timer Watchdog Enable Register
OIER			   EQU   (0x40A0001C)  ; OS Timer Interrupt Enable Register

;
; Power Manager Registers
;
PMCR			   EQU   (0x40F00000)  ; Power Manager Control Register
PSSR			   EQU   (0x40F00004)  ; Power Manager Sleep Status Register
PSPR			   EQU   (0x40F00008)  ; Power Manager Scratch Pad Register
PWER			   EQU   (0x40F0000C)  ; Power Manager Wake-up Enable Register
PRER			   EQU   (0x40F00010)  ; Power Manager GPIO Rising-Edge Detect Enable Register
PFER			   EQU   (0x40F00014)  ; Power Manager GPIO Falling-Edge Detect Enable Register
PEDR			   EQU   (0x40F00018)  ; Power Manager GPIO Edge Detect Status Register
PCFR			   EQU   (0x40F0001C)  ; Power Manager General Configuration Register
PGSR0			   EQU   (0x40F00020)  ; Power Manager GPIO Sleep State Register for GP[31-0]
PGSR1			   EQU   (0x40F00024)  ; Power Manager GPIO Sleep State Register for GP[63-32]
PGSR2			   EQU   (0x40F00028)  ; Power Manager GPIO Sleep State Register for GP[84-64]
RCSR			   EQU   (0x40F00030)  ; Reset Controller Status Register

;
; Memory Controller Registers
;
MDCNFG			   EQU   (0x48000000)  ; SDRAM Configuration Register 0
MDREFR			   EQU   (0x48000004)  ; SDRAM Refresh Control Register
MSC0			   EQU   (0x48000008)  ; Static Memory Control Register 0
MSC1			   EQU   (0x4800000C)  ; Static Memory Control Register 1
MSC2			   EQU   (0x48000010)  ; Static Memory Control Register 2
MECR			   EQU   (0x48000014)  ; Expansion Memory (PCMCIA/Compact Flash) Bus Configuration
SXLCR			   EQU   (0x48000018)  ; LCR value to be written to SDRAM-Timing Synchronous Flash
SXCNFG			   EQU   (0x4800001C)  ; Synchronous Static Memory Control Register
SXMRS			   EQU   (0x48000024)  ; MRS value to be written to Synchronous Flash or SMROM
MCMEM0			   EQU   (0x48000028)  ; Card interface Common Memory Space Socket 0 Timing
MCMEM1			   EQU   (0x4800002C)  ; Card interface Common Memory Space Socket 1 Timing
MCATT0			   EQU   (0x48000030)  ; Card interface Attribute Space Socket 0 Timing Configuration
MCATT1			   EQU   (0x48000034)  ; Card interface Attribute Space Socket 1 Timing Configuration
MCIO0			   EQU   (0x48000038)  ; Card interface I/O Space Socket 0 Timing Configuration
MCIO1			   EQU   (0x4800003C)  ; Card interface I/O Space Socket 1 Timing Configuration
MDMRS			   EQU   (0x48000040)  ; MRS value to be written to SDRAM
BOOT_DEF		   EQU   (0x48000044)  ; Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL

;
; Bluetooth UART (BTUART)
;
BTUART		       EQU   BTRBR
BTRBR		       EQU   (0x40200000)  ; Receive Buffer Register (read only)
BTTHR		       EQU   (0x40200000)  ; Transmit Holding Register (write only)
BTIER		       EQU   (0x40200004)  ; Interrupt Enable Register (read/write)
BTIIR		       EQU   (0x40200008)  ; Interrupt ID Register (read only)
BTFCR		       EQU   (0x40200008)  ; FIFO Control Register (write only)
BTLCR		       EQU   (0x4020000C)  ; Line Control Register (read/write)
BTMCR		       EQU   (0x40200010)  ; Modem Control Register (read/write)
BTLSR		       EQU   (0x40200014)  ; Line Status Register (read only)
BTMSR		       EQU   (0x40200018)  ; Modem Status Register (read only)
BTSPR		       EQU   (0x4020001C)  ; Scratch Pad Register (read/write)
BTISR		       EQU   (0x40200020)  ; Infrared Selection Register (read/write)
BTDLL		       EQU   (0x40200000)  ; Divisor Latch Low Register (DLAB = 1) (read/write)
BTDLH		       EQU   (0x40200004)  ; Divisor Latch High Register (DLAB = 1) (read/write)

;
; Standard UART (STUART)
;
STUART			   EQU	 STRBR
STRBR			   EQU	 (0x40700000)  ; Receive Buffer Register (read only)
STTHR			   EQU	 (0x40700000)  ; Transmit Holding Register (write only)
STIER			   EQU	 (0x40700004)  ; Interrupt Enable Register (read/write)
STIIR			   EQU	 (0x40700008)  ; Interrupt ID Register (read only)
STFCR			   EQU	 (0x40700008)  ; FIFO Control Register (write only)
STLCR			   EQU	 (0x4070000C)  ; Line Control Register (read/write)
STMCR			   EQU	 (0x40700010)  ; Modem Control Register (read/write)
STLSR			   EQU	 (0x40700014)  ; Line Status Register (read only)
STMSR			   EQU	 (0x40700018)  ; Reserved
STSPR			   EQU	 (0x4070001C)  ; Scratch Pad Register (read/write)
STISR			   EQU	 (0x40700020)  ; Infrared Selection Register (read/write)
STDLL			   EQU	 (0x40700000)  ; Divisor Latch Low Register (DLAB = 1) (read/write)
STDLH			   EQU	 (0x40700004)  ; Divisor Latch High Register (DLAB = 1) (read/write)

;
; Hardware UART (HWUART)
;
HWUART			   EQU   HWRBR
HWRBR			   EQU   (0x41600000)  ; Receive Buffer Register (read only)
HWTHR			   EQU   (0x41600000)  ; Transmit Holding Register (write only)
HWIER			   EQU   (0x41600004)  ; Interrupt Enable Register (read/write)
HWIIR			   EQU   (0x41600008)  ; Interrupt ID Register (read only)
HWFCR			   EQU   (0x41600008)  ; FIFO Control Register (write only)
HWLCR			   EQU   (0x4160000C)  ; Line Control Register (read/write)
HWMCR			   EQU   (0x41600010)  ; Modem Control Register (read/write)
HWLSR			   EQU   (0x41600014)  ; Line Status Register (read only)
HWMSR			   EQU   (0x41600018)  ; Modem Status register
HWSPR			   EQU   (0x4160001C)  ; Scratch Pad Register (read/write)
HWISR			   EQU   (0x41600020)  ; Infrared Selection Register (read/write)
HWFOR			   EQU   (0x41600024)  ; FIFO Occupancy register (read-only)
HWABR			   EQU   (0x41600028)  ; Autobaud Control register (read/write)
HWACR			   EQU   (0x4160002C)  ; Autobaund Count register
HWDLL			   EQU   (0x41600000)  ; Divisor Latch Low Register (DLAB = 1) (read/write)
HWDLH			   EQU   (0x41600004)  ; Divisor Latch High Register (DLAB = 1) (read/write)

;
; MMC controller
;
MMCSTRPCL		   EQU	  (0x41100000)
MMCSTAT			   EQU	  (0x41100004)
MMCCLKRT		   EQU	  (0x41100008)
MMCCMDAT		   EQU	  (0x41100010)
MMCRESTO		   EQU	  (0x41100014)
MMCBLKLEN		   EQU	  (0x4110001c)
MMCCMD			   EQU	  (0x41100030)
MMCARGH			   EQU	  (0x41100034)
MMCARGL			   EQU	  (0x41100038)
MMCRES			   EQU	  (0x4110003c)
MMCIMASK		   EQU	  (0x41100028)
MMCIREG			   EQU	  (0x4110002c)
MMCRXFIFO		   EQU	  (0x41100040)
MMCTXFIFO		   EQU	  (0x41100044)
MMCNUMBLK		   EQU	  (0x41100020)

;
; SSP
;
BV_SSCR0_1		     EQU   (0x41000000)
BV_SSCR1_1  	     EQU   (0x41000004)		; SSP1 Control register 1
BV_SSSR_1   	     EQU   (0x41000008)		; SSP1 Status register
BV_SSITR_1  	     EQU   (0x4100000C)		; SSP1 Interrupt Test register
BV_SSDR_1   	     EQU   (0X41000010)		; SSP1 Data Write Register/SSP1 Data Read register
BV_SSTO_1   	     EQU   (0x41000028)		; SSP1 Time Out register
BV_SSPSP_1  	     EQU   (0x4100002c)		; SSP1 Programmable Serial Protocol

SSCR0_SCR		     EQU   (1<<8)
SSCR0_SSE   	     EQU   (1<<7)
SSCR0_FRF   	     EQU   (1<<4)
SSCR0_DSS   	     EQU   (1<<0)

SSCR1_RX_THRESSHOLD  EQU   (1<<10)
SSCR1_TX_THRESSHOLD  EQU   (1<<6)
SSCR1_SPH            EQU   (1<<4)
SSCR1_SPO            EQU   (1<<3)

SSSR_RFL             EQU   (1<<12)
SSSR_TFL             EQU   (1<<8)
SSSR_BSY             EQU   (1<<4)
SSSR_RNE             EQU   (1<<3)
SSPSP_DUMMY_STOP     EQU   (1<<23)
SSPSP_SCMODE         EQU   (1<<0)
SSP_FIFO_DEEP        EQU   16      ; both RX & TX

;
; I2C control registers
;
BV_IBMR        		 EQU   (0x40301680)          ; Bus Monitor register
BV_IDBR        		 EQU   (0x40301688)          ; Data Buffer register
BV_ICR         		 EQU   (0x40301690)          ; Control register
BV_ISR         		 EQU   (0x40301698)          ; Status register
BV_ISAR        		 EQU   (0x403016A0)          ; Slave Address register

; I2C
I2C_ICR_UR           EQU   (1<<14)               ; Unit Reset
I2C_ICR_ALDIE        EQU   (1<<12)               ; Arbitration-Loss-Detected interrupt enable
I2C_ICR_GCD          EQU   (1<<7)                ; General Call Disable
I2C_ICR_IUE          EQU   (1<<6)                ; I2C Unit Enable
I2C_ICR_SCLEA        EQU   (1<<5)                ; SCL Enable for master-mode operation
I2C_ICR_MA           EQU   (1<<4)                ; Master Abort without transmitting another data byte
I2C_ICR_TB           EQU   (1<<3)                ; Transfer Byte
I2C_ICR_ACKNAK       EQU   (1<<2)                ; '0' for ACK & '1' for NAK
I2C_ICR_STOP         EQU   (1<<1)                ; A STOP condition after next data byte
I2C_ICR_START        EQU   (1<<0)                ; Initiate a START condition

I2C_ISR_BED          EQU   (1<<10)               ; Bus Error Detected
I2C_ISR_IRF          EQU   (1<<7)                ; IDBR Receive Full
I2C_ISR_ITE          EQU   (1<<6)                ; IDBR Transmit Empty
I2C_ISR_ALD          EQU   (1<<5)                ; Arbitration Loss Detected
I2C_ISR_IBB          EQU   (1<<3)                ; I2C Bus Busy
I2C_ISR_UB           EQU   (1<<2)                ; Unit Busy

;
; I2S control registers
;
BV_SACR0        	 EQU   (0x40400000)          ; Global Control register
BV_SACR1        	 EQU   (0x40400004)          ; Serial Audio I2S/MSB-Justified Control register
BV_SASR0        	 EQU   (0x4040000C)          ; Serial Audio I2S/MSB-Justified Interface and FIFO Status register
BV_SAIMR        	 EQU   (0x40400014)          ; Serial Audio Interrupt Mask register
BV_SAICR        	 EQU   (0x40400018)          ; Serial Audio Interrupt Clear register
BV_SADIV        	 EQU   (0x40400060)          ; Audio clock divider register. See section 22.3 Serial Audio Clocks and Sampling frequencies on page 22-7.
BV_SADR         	 EQU   (0x40400080)          ; Serial Audio Data Register (TX and RX FIFO access register).

;
; I2S
;
SACR0_RFTH           EQU   (1<<12)
SACR0_TFTH           EQU   (1<<8)
SACR0_RST            EQU   (1<<3)
SACR0_BCKD           EQU   (1<<2)
SACR0_ENB            EQU   (1<<0)

SACR1_DRPL           EQU   (1<<4)
SACR1_DREC           EQU   (1<<3)

SASR0_RFL            EQU   (1<<12)
SASR0_TFL            EQU   (1<<8)
SASR0_OFF            EQU   (1<<7)
SASR0_BSY            EQU   (1<<2)
SASR0_RNE            EQU   (1<<1)
SASR0_TNF            EQU   (1<<0)

I2S_SAM_FEQ_48       EQU   0x0C
I2S_SAM_FEQ_44       EQU   0x0D
I2S_SAM_FEQ_22       EQU   0x1A
I2S_SAM_FEQ_16       EQU   0x24
I2S_SAM_FEQ_11       EQU   0x34
I2S_SAM_FEQ_8        EQU   0x48
I2S_FIFO_DEEP        EQU   16         ; both RX & TX

;
; IRQ
;
IER_DMAE			 EQU   (1 << 7)	  ; DMA Requests Enable
IER_UUE				 EQU   (1 << 6)	  ; UART Unit Enable
IER_NRZE			 EQU   (1 << 5)	  ; NRZ coding Enable
IER_RTIOE			 EQU   (1 << 4)	  ; Receiver Time Out Interrupt Enable
IER_MIE				 EQU   (1 << 3)	  ; Modem Interrupt Enable
IER_RLSE			 EQU   (1 << 2)	  ; Receiver Line Status Interrupt Enable
IER_TIE				 EQU   (1 << 1)	  ; Transmit Data request Interrupt Enable
IER_RAVIE			 EQU   (1 << 0)	  ; Receiver Data Available Interrupt Enable

IIR_FIFOES1			 EQU   (1 << 7)	  ; FIFO Mode Enable Status
IIR_FIFOES0			 EQU   (1 << 6)	  ; FIFO Mode Enable Status
IIR_TOD				 EQU   (1 << 3)	  ; Time Out Detected
IIR_IID2			 EQU   (1 << 2)	  ; Interrupt Source Encoded
IIR_IID1			 EQU   (1 << 1)	  ; Interrupt Source Encoded
IIR_IP				 EQU   (1 << 0)	  ; Interrupt Pending (active low)

; Bulverde USB register's definition
UP2OCR				 EQU   (0x40600020)
UDCCR       		 EQU   (0x40600000)
UDCICR0     		 EQU   (0x40600004)
UDCICR1     		 EQU   (0x40600008)
UDCISR0     		 EQU   (0x4060000c)
UDCISR1     		 EQU   (0x40600010)
UDCFNR      		 EQU   (0x40600014)

UDCCSRA     		 EQU   (0x40600104)
UDCCSRB     		 EQU   (0x40600108)

; Omit endpoint C~X
;
UDCBCRA      		 EQU   (0x40600204)
UDCBCRB      		 EQU   (0x40600208)

; Omit endpoint C~X
;
UDCDRA       		 EQU   (0x40600304)
UDCDRB       		 EQU   (0x40600308)

; Omit endpiont C~X
;
UDCCRA      		 EQU   (0x40600404)
UDCCRB      		 EQU   (0x40600408)

;USB register bit definitions
UDCCR_UDE            EQU   (1 << 0)
UDCCR_UDA            EQU   (1 << 1)
UDCCR_UDR            EQU   (1 << 2)
UDCCR_EMCE           EQU   (1 << 3)
UDCCR_SMAC           EQU   (1 << 4)
UDCCR_AAISN          EQU   (1 << 5)
UDCCR_AIN            EQU   (1 << 8)
UDCCR_ACN            EQU   (1 << 11)
UDCCR_DWRE           EQU   (1 << 16)

UDCICR0_IE0          EQU   (1 << 0)
UDCICR0_IEA          EQU   (1 << 2)
UDCICR0_IEB          EQU   (1 << 4)

; Omit endpoint C~X
UDCICR1_IERS 	     EQU   (1 << 27)
UDCICR1_IESU 	     EQU   (1 << 28)
UDCICR1_IERU 	     EQU   (1 << 29)
UDCICR1_IESOF	     EQU   (1 << 30)
UDCICR1_IECC 	     EQU   (1 << 31)

UDCISR0_IR0  	     EQU   (1 << 0)
UDCISR0_IRA  	     EQU   (1 << 2)
UDCISR0_IRB  	     EQU   (1 << 4)

; Omit endpiont C~X
UDCISR1_IRRS        EQU    (1 << 27)
UDCISR1_IRSU        EQU    (1 << 28)
UDCISR1_IRRU        EQU    (1 << 29)
UDCISR1_IRSOF       EQU    (1 << 30)
UDCISR1_IRCC        EQU    (1 << 31)

UDCCSR0_OPC         EQU    (1 << 0)
UDCCSR0_IPR         EQU    (1 << 1)
UDCCSR0_FTF         EQU    (1 << 2)
UDCCSR0_DME         EQU    (1 << 3)
UDCCSR0_SST         EQU    (1 << 4)
UDCCSR0_FST         EQU    (1 << 5)
UDCCSR0_RNE         EQU    (1 << 6)
UDCCSR0_SA          EQU    (1 << 7)

UDCCSR_FS           EQU    (1 << 0)
UDCCSR_PC           EQU    (1 << 1)
UDCCSR_TRN          EQU    (1 << 2)
UDCCSR_DME          EQU    (1 << 3)
UDCCSR_SST          EQU    (1 << 4)
UDCCSR_FST          EQU    (1 << 5)
UDCCSR_BNE          EQU    (1 << 6)
UDCCSR_BNF          EQU    (1 << 6)
UDCCSR_SP           EQU    (1 << 7)
UDCCSR_FEF          EQU    (1 << 8)
UDCCSR_DPE          EQU    (1 << 9)

UDCCRB_EE           EQU    (1 << 0)
UDCCRB_DE           EQU    (1 << 1)
UDCCRB_MPS          EQU    (1 << 2)
UDCCRB_ED           EQU    (1 << 12)
UDCCRB_ET           EQU    (1 << 13)
UDCCRB_EN           EQU    (1 << 15)
UDCCRB_AISN         EQU    (1 << 19)
UDCCRB_IN           EQU    (1 << 22)
UDCCRB_CN           EQU    (1 << 25)

UDCECR_CN_MASK		EQU    (0x3 << 25)  ; Configuration Number
UDCECR_CN_SHIFT		EQU    25
UDCECR_IN_MASK		EQU    (0x7 << 22)  ; Intertface Number
UDCECR_IN_SHIFT		EQU    22
UDCECR_AISN_MASK	EQU    (0x7 << 19) ; Alternate Interface Number
UDCECR_AISN_SHIFT	EQU    19
UDCECR_EN_MASK		EQU    (0xf << 15)  ; Endpoint Number
UDCECR_EN_SHIFT		EQU    15
UDCECR_ET_MASK		EQU    (0x3 << 13)  ; Endpoint Number
UDCECR_ET_SHIFT		EQU    13           ; Endpoint Type
UDCECR_ED			EQU    (1 << 12)    ; Endpoint Direction 1 = IN
UDCECR_ED_SHIFT		EQU    12
UDCECR_MPS_MASK		EQU    (0x3ff << 2) ; Max packet size
UDCECR_MPS_SHIFT	EQU    2
UDCECR_DE			EQU    (1 << 1)     ; Double buffer enable
UDCECR_DE_SHIFT		EQU    1
UDCECR_EE			EQU    (1 << 0)     ; Endpoint Enable

UDCECR_ED_IN		EQU    1
UDCECR_ED_OUT		EQU    0
UDCECR_DE_DBLBUF	EQU    1
UDCECR_DE_SGLBUF	EQU    0
UDCECR_ET_INT		EQU    0x3          ; Endpoint Type - Interrupt
UDCECR_ET_BULK		EQU    0x2          ; Endpoint Type - Bulk
UDCECR_ET_ISO		EQU    0x1          ; Endpoint Type - isochronous

;
; DMA
;
DCSR_BASE		    EQU    0x40000000
DDADR_BASE		    EQU    0x40000200
DSADR_BASE		    EQU    0x40000204
DTADR_BASE		    EQU    0x40000208
DCMD_BASE		    EQU    0x4000020c

DRCMRRRMMC	        EQU    (0x40000154)
DRCMRTRMMC	        EQU    (0x40000158)
DINT			    EQU    (0x400000f0)

;
; PWM
;
PWMCR0 	            EQU    (0x40b00000)
PWMDCR0             EQU    (0x40b00004)
PWMPCR0             EQU    (0x40b00008)
PWMCR_SD	        EQU    (1<<6)
PWMDCR_FD	        EQU    (1<<10)

      END
